The present invention relates generally to a high speed voltage-controlled ring oscillator and, in particular, to an improved high speed voltage-controlled ring oscillator system and method having xe2x80x9clook-aheadxe2x80x9d interpolation.
Voltage-controlled oscillators (VCOs) generate an oscillating signal at a frequency proportional to an externally applied voltage. These types of circuits are useful for tracking and matching signal frequencies as they shift due to thermal variations, power supply fluctuations, and other sources of frequency phase-shifts. VCOs are found particularly often in phase-locked loop circuits (PLL) used for clock generation and synchronization. Such PLL circuits are often employed in receivers, transceivers, frequency modulators, frequency demodulators, modems and various other high frequency electrical devices.
FIG. 1 illustrates, in block format, a conventional ring oscillator VCO 100. Ring VCO includes a chain of voltage-controlled delay stages, 110, 120, 130 and 140, coupled together in a negative feedback loop 150. Each delay stage includes a delay element, 160, 170, 180 and 190, and an analog summer, 165, 175, 185 and 195. As is common in conventional ring VCOs, the delay element typically includes one or more buffers and/or inverters. The delay element contributes to a delay of a signal propagated through VCO 100 and consequently limits a maximum frequency over which VCO 100 can operate. In general, the circuit will oscillate with a period, T, equal to the voltage-controlled cell delay multiplied by twice the number of delay stages (i.e., the signal must propagate through the inverting path twice to return to its original value), as provided by the following Equation 1:
T=tp2Nxe2x80x83xe2x80x83(1) 
where: tp is the voltage-controlled cell delay; and N is the number of delay stages in the loop.
Consequently, the frequency of oscillation, f, of the circuit is inversely proportional to the period as provided by the following Equation 2:                     f        =                              1            /            T                    =                      1                                          t                p                            ⁢              2              ⁢              N                                                          (        2        )            
As the operating frequency for electrical devices continues to rise, e.g., high frequency communication devices, circuitry within the devices must be able to accommodate and operate in the higher frequency bandwidths. In other words, an operating frequency in the gigahertz (GHz) range requires various electrical devices to reduce internal delay times in order to accommodate this high frequency. It is clear from Equation 2, that as the operating frequency increases, the allowable delay time decreases in an inversely proportional manner.
The delay stages of the ring oscillators may be configured in a variety of ways. For example, varactor tuning of an RC delay, bias modulation and delay interpolation may be used to form a variable delay stage. Of these various configurations, interpolation is often desirable because the delay stages provide a relatively linear output over a relatively wide tuning range. However, ring oscillators that use interpolation techniques often require an additional delay stage or element which is generally undesirable.
With continued reference to conventional ring VCO 100, a four stage delay interpolation system is shown. The minimum loop delay achievable with this system corresponds to the delay from the stages and the maximum delay is twice the number of stages. The minimum oscillator period is twice the loop delay, or equivalently 8 delays, and the maximum oscillator period is equivalently 16 delays.
Accordingly, an improved ring VCO having fewer delay stages for high speed operation, especially in higher frequencies, is desired. In addition, an improved system and method for signal interpolation for a high speed ring VCO is desired.
The present invention overcomes the problems outlined above and provides an improved high speed voltage-controlled ring oscillator system. In particular, the present invention provides a voltage-controlled oscillator having a plurality of interpolation stages coupled together in a xe2x80x9clook-aheadxe2x80x9d interpolation configuration. Each interpolation stage includes a signal output and two signal inputs, such that a first input represents the signal output of the immediately previous stage, and the second input represents the signal output of the immediately previous second stage.
In this manner, relative to a delay interpolation VCO, look-ahead interpolation eliminates a delay element of each stage, thereby providing a high speed voltage-controlled ring oscillator system capable of achieving a higher maximum operating frequency.